Synthesis Questionnaries

Here i am writing some questions which are totally based on my experience which i have come across during my professional career until now. I would keep appending this as i encounter any new one. I would also like to thank some of my friends from the same domain who have given me some inputs as well. I would also motivate you to share your experience, it can be a single question in any domain. After all "Sharing knowledge is the best way to learn". Please leave a comment and share to maximum of your friends in order to let them think and to enhance their knowledge.


Question: What are the inputs required for synthesis, in order to generate a netlist?
Answer > The following diagram depicts the required inputs used in synthesis to generate a netlist.
Question: How you will find the virtual clock period corresponding to the input/output ports (which need to be constrained) when external design parameters (connected block info) are not known?
Answer > When external I/O info is not available specially for the clock, then in this case the fanout of input port can be traced (upto level 1 flop) for endpoint. After getting the info of connected flop to the port, the clock information of flop can be easily obtained and the same clock period can be used as period of virtual clock to constraint the input port.
Question: How Synthesis results will change when max_transition value is changed. (as compared to the original runs)
Answer > When max_trans value is changed with respect to the original value, this will impact the synthesis results like switching power, delay. max_transition time signifies the time which a signal takes to change its state. A slow input transition time (more time) will slow the rate at which the cell’s transistors can change state logic 1 to logic 0 (or logic 0 to logic 1), thereby increasing the delay of the logic gate. Also if the transition time is more then it means the time for which both the transistors turn-on is also more which leads to more switching power. so synthesis results mainly delay and power will change accordingly.
Question: How you can propagate block level constraints to top level.
Answer > For the top level only exceptions are required to be propagated like multi-cycle path, false paths, case analysis etc. Different companies uses different mechanism for this propagation. SDC Promotion is one of the technique where tool will take all the exceptions from IP level sdc and will convert into top level. Other technique is xml based approach, where the exception will be defined under a section <exception> (let's say) at block level. All the exceptions which are defined should have a prefix hier_prefix (lets' say) and the value of this should be "". This variable is just used to maintain the proper hierarchy name. At the top level, this variable should be initialized with the proper hierarchy of block (path of IP instance).and also the important thing here to note is that all the exceptions which has -from and -to option in command should be replaced by -through option. since at top level this will be part of intermediate path not the start or end point.
Question: How you will detect if you missed some clock definitions on ports/pins during synthesis while defining constraints.
Answer > If someone has missed some clock definitions on the input ports in sdc and proceeded for synthesis then there is no problem in the execution of synthesis i.e netlist will be dumped out anyways. But after the netlist is dumped out one should check the quality checks on this dumped netlist. One of such check is modal coverage report, which reports all the unconstrained end points in the design. If the clock is not reaching to the flop CK pin then the input of such flops will be appearing in the report. The other way is to check explicitly the no-clock and multi-clock report after the synthesis.
Question: What are different area and power optimizing techniques used during synthesis.
Answer > There are different techniques and settings (tool specific) which are used for saving area and power.
Area optimization:
    - set_max_area -ignore_tns 0 --> it will give more timing violations but will try to reduce area amap. Not recommended
     - set_max_area 0 --> will give less timing violation
    - Compile - map_effort high -incremental_compile ---> map_effort high will take more compilation time but will give better results. (design compiler specific)
    - Incremental compile will start from current map and will optimize where there are violations.
    - We also use MBR cells (multi-bit register) for some area saving.
Power optimization:
    - Dynamic power: Clock gating technique is used to save dynamic power wastages
    - Leakage Power: HVT cells are used to reduce leakage and whenever LVT cell is used. we use sleep cell for controlling the leakage.
    - We also use the power domains and isolation cells for saving the power in SoC.
    - By scaling supply voltage
Question: How you can model a wire delay during synthesis.
Answer > The wire delay can be modeled using the wire delay model which will account for the RC value of interconnect. The model also specifies a per length resistance, capacitance and area and a statistical mapping from the fanout to wire length. Using wire length and R/C value, delay value can be computed. RC delay is calculated depending on the interconnect model. There are three types of models namely Best case tree, Balanced tree and Worst case tree. Wire-load models are generally defined in .lib
Question: What is boundary optimization w.r.t synthesis.
Answer > Boundary optimization during synthesis include the following optimizations,
  • Constant propagation across hierarchies
  • Removing undriven or unloaded logic connected
  • Collapsing equal and opposite pins.
  • Hierarchical pin inversion
  • Rewiring of equivalent signals across hierarchy. 
Question: What are the minimal constraints required for synthesis.
Answer > The minimal constraints required for synthesis includes the clock definition, constraining input and output ports with delays, setting input transition on input ports and output load on output ports. (exceptions like multicycle path, false path, case analysis is equally important for correct timing analysis and in run time reduction, but one can do synthesis without these exceptions as well).
Question: What is difference between lint checks at RTL level and check_design during synthesis.
Answer > check_design in synthesis provides information on undriven and multi-driven ports and pins, unloaded sequential elements and ports, unresolved references, constants connected ports and pins, any assign statements and preserved instances in the given design. In addition, the command can report any cells that are not in both .lib and the physical libraries (LEF files). By default, if you do not specify an option, the check_design command reports a summary table with this information.
Question: What are the different commands used for synthesis in RC flow versus DC flow. or compare the synthesis flow for RC and DC tool.
Answer > Please refer to link for sample script of RC and DC flow.
Question: What should be done if you are seeing big violations in timing reports after synthesis. or in other words how to fix timing violations after synthesis.
Answer > Generally after synthesis one should check the timing reports (pre-sta reports). If you are seeing a big setup violations then,
  • One should look for the missing constraints (if-any) like multi-cycle path, false path etc. 
  • Its always recommended to start the synthesis with high-Vt (HVT) cells so as to reduce the leakage power. If you are able to close the timing with the HVT cells then its ok otherwise open LVT cells during synthesis, this will help in reducing the timing violation. 
  • Another method is creating path groups. We can create path groups and assign weightage to those path so that tool will try to fix them separately. 
  • Specify critical range: If we don't specify critical range, it works only on WNS but if critical range is specified then it works on all path which are below the specified range and it reduces TNS also.
  • Enable boundary optimization, but it optimize area also.
  • Try incremental compile (with high effort).
  • Enable register retiming: Register retiming is the process by which the tool moves registers through combinational gates to improve timing.
  • Pipeling.
  • Remove area constraints (if any).
Question: How Wire-load delay model (WLM) works.
Answer > A wire-load model is what the synthesis tool uses to estimate wire characteristics (e.g. interconnect delay) in the absence of physical layout data. For a wire with a given fanout, the wire-load model specifies the capacitance, resistance, and area of the wire.
Question: What you generally check when synthesis is over.
Answer > When synthesis is over one should check for the QoR report, which will give a snapshot of various timing details, area info, power info etc. Ideally there will be different detailed reports generated for area (sequential/combinational count), timing (clock group wise TNS, WNS) and power. There are some sanity checks also which should be performed in the generated netlist like modal coverage, no-clock/multi-clock report etc to check the correctness of netlist.  Please refer to for more details. 
Question: Why inferring a latch is an error during synthesis.
Answer > Inferred latches can serve as a 'warning sign' that the logic design might not be implemented as intended. A crucial if-else or case statement might be missing from the design. Latches can lead to timing issues and race conditions. They may lead to combinatorial feedback - routing of the output back to the input - which can be unpredictable. To avoid creating inferred latches,
  • Include all the branches of an if or case statement
  • Assign a value to every output signal in every branch
  • Use default assignments at the start of the procedure, so every signal will be assigned.
Transparent latches will appear if you write a combinational process or always block where an output is not assigned under all possible input conditions. In other words, it is possible for one of the inputs to change without affecting the output. In synthesis jargon, this is known as incomplete assignment.
Question: What are the RTL quality checks which are performed during synthesis.
Answer > While elaborate command does the elaboration of rtl and reports for any issue, apart from this as mentioned earlier check_design is a mandatory step which needs to be run in order to get the summary of various checks which are performed ar RTL level. These includes unconnected ports, constant-valued ports, cells with no input or output pins, mismatches between a cell and its reference,
multiple driver nets, connection class violations, and recursive hierarchy definitions etc.
Question: Is Assign statement synthesizable?
Answer > Assign and deassign of reg data types is not synthesizable but assign on wire data type is synthesizable. Assign is a good candidate for simple combinational logic like mux "assign out_val = sel ? in_1 : in_2;
Question: what is difference between logical and Physical synthesis?
Question: Why cann't CTS be a part of physical synthesis when we have information about the placement?
Answer > Yes it can be a part of physical synthesis. 
Question: What are Design Rule Checks (DRC) with respect to synthesis.
Answer > Design rule checks (DRC) in synthesis comprises of the following: max_transition (longest time allowed for a driving pin of a net to change its logic vaule), max_fanout (maximum fanout of a driving pin), max/min_capacitance (The maximum (and minimum) total capacitive load that an output pin can drive. The total capacitance comprises of load pin capacitance and interconnect capacitances). These DRC have the highest priority in the design.
Question: What "elaboration" command does w.r.t synthesis?
Answer > Elaboration does the following : Builds data structure, Infers register in the design, Performs high level HDL optimization such as dead code removal, check semantics etc.
Question:What are high fanout nets?
Answer > High fanout nets are generally those nets which drive more number of loads. Usually in a design the HFN (high fanout nets) are clock, reset or test enable nets. Basically these caters to multiple loads in a design. The delay involved in these nets will be huge. so tool will buffer these nets.Refer to link
Question:What is difference between Logical Exclusive, Physical Exclusive and Asynchronous timing constraints in context to Synthesis?
Answer > There are three different type of constraints which are used with the set_clock_groups,
Physically_Exclusive: Means Timing paths between these clock domains are false, but only one clock can exist in the design at the same time. Timing tool ETS/Tempus will filter out the SI interactions of nets/paths between these groups. if the clocks are exclusive, then there should be no SI victim/aggressor interaction at all between nets clocked by physically excluded clocks.
If two clocks are asynchronous, it means that they don't have any phase relationship among them at all. So instead of using definite timing windows based on arrival times/skew etc, the timing tool will use infinite timing windows when calculating aggressors and victims, therefore you will see maximum SI impact.
Logically_Exclusive: Logically exclusive means the timing paths between these clock domains are false, but both clocks can exist in the design at the same time, so SI interactions between paths in these domains should still be considered. However crosstalk analysis will be done with regular timing windows based on arrival times/skew etc.
Question:Why latches should be avoided in a design?
Answer > In digital logic, latches hold the value of a signal until a new value is assigned. Latches should be avoided whereas possible in the design and flip-flops should be used instead. As shown in Fig below if both the X and Y were to go high, and since these are level triggered, both the Latches would be enabled resulting in the circuit to oscillate. Latches can cause various difficulties in the design. Although latches are memory elements like registers, they are fundamentally different. When a latch is in a feed-through mode, there is a direct path between the data input and the output. Glitches on the data input can pass to the output.

Question:What are timing loops?
Answer > When you have the timing path from output to input again through some combinational cells, then it creates a timing loop
Question:How to break a timing loop?
Answer > Using set_disable_timing, or manually doing disconnect and connect.
Question:What are different timing arcs in a Flop ?
Answer > D--> CLK and CLK --> Q
Question:What happens to a flop when you have the D --> Q defined as timing arc?
Answer > The flop will work as a computational cell, Probably as a buffer.


  1. Replies
    1. Thanks Bala. keep checking out the site, we will keep updating this with the latest in the industry.

  2. you really are a genius crystal clear explanation.
    can you please upload all the soc concepts

    1. Thanks Aarthi for those kind words. keep checking the blog, we are trying to cover all the topics in SoC.

  3. This comment has been removed by a blog administrator.