Monday, March 7, 2016

Multicycle Path - All You want to Know

While preparing for the constraints we usually come across the multi-cycle concept. How to set a multi-cycle path? How does it works? If i had given multi-cycle for a path with various options (setup/hold/start/end) then where setup and hold check occurs? To answer all these question please go through the following blog, it provides you with complete knowledge of multi-cycle starting with the basics.

What is a Multi-cycle Path:
Generally a combinational data path between two flip-flops takes a single clock cycle to propagate through the logic, but in some cases this can take more than a single clock cycle. In such case a data path through the combinational logic is termed as a "multi-cycle path". Although the data is being captured by a capture flop in every clock cycle but through this constraint we tell the STA tool that the required capture edge occurs only after the specified number of cycles.

If we will not define any multi-cycle path then by default the setup check occurs after the one clock cycle and hold check occurs at same edge as shown below (Note: By default hold check occurs at one edge prior to the setup check).

In case my combinational data path delay is such that it takes 3 clock cycles to propagate the data to capture flop then there should be mcp defined for setup check as (refer below figure),
set_multicycle_path 3 -setup -from [get_pins <launch_flop>/Q] -to [get_pins <capture_flop>/D]
The important point to note here is that if i have not defined the corresponding mcp constrain for hold then the default hold check applies and it says that this check will happen one cycle prior to the setup check (with mcp). so if a clock period is 5ns and i have applied the above constraint then setup check will happen at 15ns and the default hold will be checked at 10ns (one cycle prior to 15ns). Please refer below.
The combo in the path takes delay upto 3 clock cycles.

Now what is the problem with constraint defined above. Please note that although we have provided mcp constraint for setup but corresponding constraint for hold is missing. The intended hold check should be done at the same launch edge i.e 0 (launch) to 0 (capture). so the corresponding hold constraint will be,
set_multicycle_path 2 -hold -from [get_pins <launch_flop>/Q] -to [get_pins <capture_flop>/D]

So in general in most of the designs, a mcp of setup of 'N' clock cycles should be provided with corresponding mcp hold with '(N-1)' clock cycles. What happens when a multi-cycle setup of N is specified but the corresponding N-1 multi-cycle hold is missing? In such a case, the hold check is performed on the edge one cycle prior to the setup capture edge.

When we do timing analysis, we encounter such cases where the launch and capture clock periods are integral multiples to each other. In other words we can say in one case the launch clock period is more than capture clock period and vice-versa. If launch clock period is more than capture clock period then we can say that the path is from slow clock to faster clock and if launch clock period is less than capture clock period then the path can be termed as a fast clock to slow clock path. Now in both the cases where to check the setup and hold? If we have defined multi-cycle path then in this case where setup and hold check will be performed? All these will be discussed here in subsequent article. Let's start with slow to fast clock path.

Slow to Fast Setup and Hold Check:
As said earlier if launch clock period is more than capture clock period then we can say that the path is from slow clock to faster clock. first analyze the following path in the figure. We have a launch flop (DL as input , QL as output, CKL as clock) and a capture flop (DC as input, QC as output, CKC as clock).

Clock definition is common for launch and capture flop except that before feeding to launch flop the clock goes through frequency divider 4 circuit. So if i need to provide a clock definition then i would be defining as the following,
create_clock -name CKL -period 20 -waveform {0 10} [get_ports CKL]
create_clock -name CKC -period 5 -waveform {0 2.5} [get_ports CKC]

When the clock frequencies are different for the launch flip-flop and the capture flip-flop, STA is performed by first determining a common base period. The faster clock is expanded so that a common period is obtained. For the above design the message which will be displayed will be like,
"Expanding clock 'CKC' to base period of 20.00"

By default the setup check will be done at every edge of capture clock (e.g 5,10,15,20 w.r.t to launch at 0ns in this case) but the tool will take most constraining setup edge check (pessimistic one) which is very next capture edge i.e 5. So the setup check will happen between launch at 0ns and capture at 5ns. And as said earlier that the hold checks are related to setup check and which will happen at one edge prior to the setup edge so in this case the hold check will be happening at 0ns of capture clock (Refer to above figure).

But do you think that the above scenario is correct as per the design? No, because the launch data is available only after the 4 clock cycle of capture clock. Our intention is not to capture the data at very next edge of capture clock CKC i.e at 5ns, but to capture at the 4th edge of clock CKC. In order to achieve this we need to provide the following multi-cycle path constraint.
set_multicycle_path 4 -setup -from [get_clocks CKL] -to [get_clocks CKC] -end

 -end option specifies that the multi-cycle of 4 refers to the end point or the capture clock.
So with this constraint the setup check edge is modified and shifted to the following edge as shown below,

But again there is a problem with hold check in above figure. we have provided the mcp constraint for setup but corresponding hold constraint is missing. In the above scenario the hold check will be done at 15ns of capture clock CKC (one edge prior to setup check). so there will be many hold violations in the design because of these types of missing mcp constraints. The proper constraint for hold would be,
set_multicycle_path 3 -hold -from [get_clocks CKL] -to [get_clocks CKC] -end

With the additional multi-cycle hold specification, the clock edge CKC used for hold timing checks is moved back three clock cycles as shown below and following diagram shows the timing checks when proper mcp constraint given for both the setup and hold in case of slow to fast clock crossing.


Note: In case of slow to fast clock domain crossing it is always recommended to use -end option with multi-cycle path constraint. With this option, the setup and hold checks are adjusted based upon the clock cycles of the fast (capture) clock. And always provide corresponding multi-cycle path constraint for hold also w.r.t to setup.

Fast to Slow Setup and Hold Check:
If launch clock period is less than capture clock period then we can say that the path is from fast clock to slow clock. Refer to the following figure which shows once such scenario. Now we have frequency divider which is there in the path of capture clock.

For the above circuit, the clock definitions can be given as,
create_clock -name CKC -period 20 -waveform {0 10} [get_ports CKC]
create_clock -name CKL -period 5 -waveform {0 2.5} [get_ports CKL]

As we can see the period of the launch clock CKL is 5 and that of capture clock CKC is 20. so in this case the launch will be happening at 0ns, 5ns, 10ns, 15ns within a window of first capture edge which is at 20ns. so the possible setup check can happen at the shown edges but hold check will be at 0ns. As said earlier the tool will take into consideration the most restrictive check which is launch at 15ns and capture at 20ns (we are saying restrictive because the timing window is small among all the checks). Also there are four hold checks possible, we have shown the most restrictive one which is at same edge.


The scenario defined above is without any multi-cycle constraint and depicts the tool behavior. However being a designer we can restrict the check as per the design and can direct the tool to check setup and hold at specific edge. If we want to relax two clock cycle with respect to fast clock and want to perform the setup check, launch at 10 and capture at 20 then the following multi-cycle constraint can be provided.
set_multicycle_path 2 -setup  -from [get_clocks CLKP] -to [get_clocks CLKM] -start

As said earlier with the mcp of setup the corresponding mcp of hold also should be defined for proper timing checks which should be (n-1) of setup. so the following hold mcp should also be defined,
set_multicycle_path 1 -hold -from [get_clocks CLKP] -to [get_clocks CLKM] -start. 

-start options signifies that the mcp is applied as per the launch clock. With the above mcp constraint the setup and hold check would be as shown below,

Note: In case of fast to slow clock domain crossing it is always recommended to use -start option with multi-cycle path constraint. With this option, the setup and hold checks are adjusted based upon the clock cycles of the fast (launch) clock. And always provide corresponding multi-cycle path constraint for hold also w.r.t to setup.

Hope the above article answered the questions from where we have started this article. Please leave the comment if u like or if u have any queries.


  1. Hi thanks for the detailed explanation .I would also like to know how we will identify/ suspect a multicycle path or false path in real time timing report physical design back end .

    1. Thanks for those words. Ideally Multicycle paths or false paths are design related. This information should come from the designer. But being an implementation engineer, before reaching out to designer, you should look at the detailed timing report. If the violation is too large in magnitude in comparison with the clock period then you should focus on the detailed report. Check the path, what actually is causing big violations? Is this only buffers (inverter pairs) or actually you have combinational cells in between. If combi cells are present and it is a part of synthesis optimization which tool did then we can say that it can be multicycle path which cannt be met in a single cycle. Either we should have pipeline for those paths or add MCP's. For false path if the clocks are asynchronous (different clock sources, PLL)we can straight away figure it out. Hope it explains.

  2. Thanks for your reply.Can you kindly do a post regarding false path ,half cycle path,virtual clocks from a physical design point of view with real time examples.

    1. Sure, these things are already under way. Soon I will be updating them. Keep checking the space.

  3. Okay Also please do a post regarding clock gating cells,power switches,retention cells ,always on cells,level shifters ,isolation cells like what all checks & precautions we need to take before placing these cells in the design .

  4. loved the way you explained, thanks for sharing.

  5. Couple of questions:
    1. Can you provide circuit required for MCP in actual hardware?
    2. Why hold check should be done at launch edge?

  6. hello,
    please give half cycle path and multi cycle path setup and hold equations?

  7. This comment has been removed by the author.

  8. Thanks for detail explanation. sir, please provide about positive to postive edge triggering for multicycle path.