Tuesday, February 9, 2016

High Fanout Synthesis

Some times we generally talk about the high fanout nets (HFN). This article discusses about the concepts related to high fanout nets, what are they? How we handle them in synthesis?

What is High Fanout Net (HFN):
Generally the High Fanout nets are those nets which drive many loads. Basically in any design we have clock nets, reset nets, test enable etc. So every sequential element in the design need this connectivity of clock, reset, test enable (in case of scannable flop). Usually these nets cater to many sequential elements so they are generally referred as high fanout nets.

How to handle HFN during Synthesis:
Now the question arises can we set any net as high fanout net. The answer is yes. During synthesis one can explicitly define the high fanout nets by using command set_max_fanout . Synthesis tool will treat all nets as HFN which has more fanout than this defined value. The delay involved in these nets will be large as it is driving many loads. you can see this by doing report timing through this net after doing synthesis. So tool will try to buffer these nets. 

Please note that this HFN buffering will not make much sense in the front-end (implementation) side since the back-end (physical design) tool will remove the buffering and will re-do synthesis at their end. So unnecessarily during synthesis we are buffering the HFN paths. Now how to avoid this.

Well general practice is to keep ideal network on these HFN, by using set_ideal_network command, so that tool will treat these networks as ideal network and will not do buffering at all. This will speed up the process and will save time and redundancy.   

Hope i am clear !! leave comment if you have any.

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