Sunday, September 25, 2016

SoC Prototyping in FPGA

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Saturday, May 7, 2016

FPGA Interview Questions and Answers


  1. What is FPGA ?

ANS : FPGA - Field Programmable Gate Array.
It is a device with programmable ‘logic blocks’ and programmable ‘interconnects’.  Logic blocks contain LUTs and CLBs which used to implement mathematical or logical functions and interconnect join them to make large design. It uses external memory to store the interconnection information. This information can be changed and device can be reprogrammed by prototype designer.

  1. Draw the general structure of FPGA ?
ANS : FPGA - Basically it consists of programmable ‘Logic Blocks’ and ‘Interconnects’.
fpga_logic_blocks_interconnects.gif
Logic Blocks contains CLB (Configurable Logic Block) and each CLB contain some LUTs (Look-Up-Table) and other logic.

  1. Explain CLB’s and LUT’s of FPGA ?
ANS : Logic Blocks primarily contain programmable CLBs and LUTs.
  1. CLB (Configurable Logic Block) - These are the main logic resource for implementing sequential as well as combinatorial circuits. A CLB elements contains a pair of ‘slices’. They don’t have direct connection to each other. Each slice has contain independent carry chain.
  2. LUT (Look Up Table) -  Each Slice contains four or six input look-up-table (LUT), storage elements, multiplexers and carry logic. These element are used to provide logic, arithmetic and  ROM functions. Some slice contains additional functions like Distributed RAM and shifting data 32-bit.

  1. Steps for FPGA Prototyping ?
ANS : Find the FPGA prototyping design flow in following link.

  1. What are the differences between FPGA and ASIC also give pros and cons ?
ANS : FPGAs (Field Programmable Gate Arrays) and ASICs (Application Specific Integrated Circuits) both have their advantages. FPGA’s are reprogrammable but costly where ASIC’s are non-programmable and application specific but cheap. Let’s look
FPGA Advantages
1.
Field Reprogrammable
Bitstream can be uploaded remotely.
2.
Simple design cycle
Tool take care of routing, placement and timing.
3.
Faster time to market
No layout, masking or fabrication needed.

ASIC Advantages
1.
Full custom capability
Device is manufactured with design specs.
2.
Lower unit cost
Generally cost is lower due to mass production.

  1. What is Synthesis ?
ANS : Synthesis is the process of translating HDL code into gates. Synthesis tools take HDL code and gives gate level netlist output for selected device. Please go through following link for more information-

  1. List of synthesizable and non-synthesizable constructs ?
ANS : Please go through following link for synthesizable and non-synthesizable constructs  information-

  1. What is DRC and difference between DRC and LVS ?
ANS : DRC : Design Rule Check
In ASIC there are some sets of rules which depends on technology used to design. Means some sets of parameters which decide where the mask should be placed, connected and routed in the layout. This check has responsibility of design to work after fab process.
In FPGA, tool (like vivado) check the correctness of the design before synthesis, which is also said DRC check.
LVS : Layout Versus Schematic
DRC ensure that layout conforms the rule required for faultless fabrication. But it is not guaranteed layout contain same circuit you desire to fab. Here the LVS check required. This process matches the netlist extracted from layout versus the original schematic or circuit.

  1. What is stuck at ZERO Means ?
ANS : Some time in ASIC due to some fault any node will permanent tie to either ‘0’. This is called Stuck at ZERO error. Similarly stuck at ONE error. To check this error we need to provide some testability in RTL.
It generally not appears in FPGA prototyping, these are tested hardware which are programmed by bit file not fabricated so probability of error is less.

  1. What is DFT and do it require in FPGA prototyping ?
ANS : DFT : Design for Testability.
Check the toggling of each flop in the design and eliminate the manufacturing error like stuck at ‘0’ or ‘1’, DFT process is used. Apart from the functional logic DFT logic are also added in design and patterns are generated so that we can test the manufacturing defects after it come from fab. Scan chain, MBIST and LBIST are the part of this test.

  1. What are MBIST and LBIST in DFT ?
ANS : BIST : Built in Self Test.
Two most common method for DFT testing are Logic BIST (LBIST) and Memory BIST (MBIST).
LBIST is design for testing random logic, which use pseudo random pattern generator (PRPG) to generate input pattern and multiple input signature register (MISR) for obtaining the response of the device for there input pattern. An incorrect MISR output indicate the defect in the device.
MBIST is design for testing memory, which use various algorithm to test memory by writing, reading and comparing. MBIST check following faults in memories
  1. Stuck-at Fault
  2. Transition Fault
  3. Coupling Fault
  4. Neighborhood Pattern Sensitive Fault
  5. Address Decoding Fault.
“March” Algorithm is most common algorithm used in industry.

  1. What are the differences between FPGA and CPLD ?
ANS : FPGA : Field Programmable Gate Array.
CPLD : Complex Programmable Logic Device.
Function of both the devices are same but difference in
  1. Capacity : Normally CPLD has less capacity than FPGA.
  2. Image Storage : CPLD can bootup by itself but FPGA has large boot image and it fetches image from SRAM.
  3. Features : CPLD only provide gates but FPGA also provides hard blocks like Block RAM, DSP, Microprocessor etc. which make FPGA more suitable for embedded systems.

  1. What is DCM, Why the are used ?
ANS : DCM : Digital Clock Manager
DCM is an electronic component which uses the feedback path to maintain the clock signal despite normal variation in operating temperature and voltage. The output of DCM gives clock with minimum skew with high fanout, because it uses global buffer for high fanout.

  1. What are differences between DLL and PLL ?
ANS : DLL : Delay Lock Loop
PLL : Phase Lock Loop
These are two technique to minimize the clock skew.
  1. PLL use voltage-controlled-oscillator (VCO) whereas DLL use delay line.
  2. PLLs are hybrid analog and digital whereas DLLs are all digital.
  3. DLL have step errors but hybrid PLL does not have it.
  4. DLL have less clock skew than PLL.

  1. What are the different modes of programming the FPGA ?
ANS : There are many modes of programming the FPGA.
  1. SRAM via JTAG or programmable cable.
  2. Flash.
  3. USB and SD-Card.

  1. What is constraint file and why we use it ?
ANS : Constraint file required for make design as per your requirements, like there is need to take out some signals to particular pins of FPGA eg. JTAG or define clocks as false path or multi-cycle path. More can find from -

  1. Name the FPGA manufacture companies ?
ANS : FPGA Companies
  1. Xilinx (~50%)
  2. Altera (~40%)
  3. Lattice Semiconductor
  4. Microsemi (Actel)
  5. QuickLogic

  1. What is the difference between ‘Hard Processor Core’ and ‘Soft Processor Core’ ?
ANS : Generally FPGA are categorized in following two ways in terms of design.
  1. Hard Processor Core - Some part of FPGA has fixed blocks like processor core and some common standard IPs. Little space for other logic implementation.
    1. Capable of work on high speed due to better optimization.
    2. But have fixed configuration and can not be altered.
  2. Soft Processor Core - Full FPGA can be used for logic. User need to implement soft processor core if required.
    1. Can be easily modified and have more logic.
    2. But limited in terms of speed of the fabric.

  1. How you can know the maximum allowable operating frequency of your design ?
ANS : Maximum allowable frequency is limit by ‘Setup Violation’ in FPGA design. Timing report generated for the given clock frequency. If minimum ‘Slack’ between two flops is positive then we can decrease the time period by that amount or increase the frequency.

  1. How you can increase the operating frequency of the design in FPGA ?
ANS : There are following ways which might use to increase the operating frequency of the design
  1. Check timing critical path and optimized it.
  2. Proper design constraint and timing constraint.
  3. Pipeline structure.

  1. What is minimum and maximum frequency of DCM in Spartan-3 and Virtex-5 series FPGA ?
ANS : Minimum and maximum frequency of DCM in
  1. Spartan-3 : 24 MHz to 248 MHz
  2. Virtex-5 : up to 550 Mhz

  1. Can CLB configured as a RAM ?
ANS : In Xilinx CLB has two slices which is Slice-L and Slice-M. Function generators (LUTs) in Slice-M can be implemented as a synchronous RAM called distributed RAM. Multiple LUTs in Slice-M can be combined in various ways to store large amount of data.

  1. What is Global Buffers, give some example ?
ANS : Global Buffer - Distribute the high fanout signals throughput.
In Xilinx FPGA there are many types of global buffers available like BUFG, BUFGMUX, BUFGCE etc. Different FPGA has limited global buffers and apart from tool user can explicitly use them also by using constraint file.

  1. Is there is any way to use the design in FPGA which has ‘setup violation’ ?
ANS : Setup violation accrue if net delay between flops are greater than Time period of the clock. So if we can increase the time period of clock such that it is greater than or equal to net delay then we can use that same FPGA design. Increase the time period means decrease in frequency so by lowering the clock frequency can make design work.

  1. Is there is any way to use the design in FPGA which has ‘hold violation’ ?
ANS : Hold violation accrue when path delay is less than the hold time of the flop. So by adding some path delay we can use the design. But that path delay should not exceed the time period of clock.

  1. What is ‘contamination delay’ in sequential circuit and difference with propagation delay ?
ANS : Contamination Delay (Tcd) : Minimum time that the logic gate will change the output based on change in input.
Propagation Delay (Tpd) : Maximum time that the logic gate will change the output based on change in input.
d4s_contamination_delay.JPG

  1. Which are the different reports we need to look while FPGA prototyping ?
ANS : At different phase of FPGA prototyping following report are generated
  1. Synthesis report after synthesis.
  2. Place & Route and
  3. Timing report after Place and route or bit file generation.

  1. Which primary information are need to look in above reports ?
ANS : Following main information need to look in synthesis report
  1. Signals or registers which are optimized or prune.
  2. Latches in the design.

Following information need to look in P&R and timing report
  1. Setup and Hold Violation.
  2. Are the clock constraints applied properly.
  3. False path and multi cycle path.
  4. Gate count.

  1. What are different type of RAMs in FPGA and how we can use them ?
ANS : Xilinx FPGA provides two options for creating memories for storing data.
  1. Distributed Memory : Array of register.
  2. Block Memory : Dedicated memory.
When synthesis tool synthesize the RTL then it can use any memory depends on your coding. Before move on to coding style first see the difference between them.
  1. When it require to make small data memory, like small buffers or registers then use distributed memory.
  2. When it require to store large amount of data, like data message buffers or large lookup table then use block memory. This memory is limited and depends on FPGA series.
We should not use distributed memory for storing large amount of data because it use large number of logic cells/flops to make register and will take large number of registers to make memory.
//Let’s see the verilog code for configure block RAM
module  B_RAM (clk, addr, we, data_in, data_out);
input clk, we ;
input [1:0]   addr ;
input   [15:0]   data_in ;
output  [15:0]  data_out ;

reg [15:0]  mem [3:0] ;
reg [15:0]  data_r ;

assign  data_out  =  data_r ;
always  @  (posedge  clk)  begin
if (we) begin
mem [addr]  <=  data_in ;
end
data_r  <=  mem [addr] ;
end
endmodule
NOTE : Initialization the RAM separately.   
  1. What is the difference between ‘reg’ and ‘wire’ ?
ANS : In HDL language ‘wire’ is which connects two nodes, it can not store data and used for designing combinational logic.
Whereas ‘reg’ can store the value and drive strength. It can use for modeling both combinational and sequential logic. Reg data type can be initial and always block.

  1. What is different type of ‘timing verification’ ?
ANS : There are two type timing verification -
  1. Dynamic timing
  2. Static Timing

  1. What does ‘timescale 1ns/1ps’ signifies ?
ANS : Timescale specify the time unit and precision of a module. It is written as
timescale  time_unit_base / precision_base
From above example ‘timescale 1ns/1ps’, the base of time unit is in nanosecond and base of precision is in picosecond. Time unit is amount of time a delay #1 represents and precision is how many decimal points of precision to use relative to the time unit.

  1. Different Debug tools used in FPGA design debugging ?
ANS : Each FPGA Tool manufacturing company will also make some tools for debugging like
  1. Chipscope - Xilinx
  2. Protolink - Synopsis
  3. On-Chip Debugging - Altera

  1. What is ‘Emulation’ and difference from ‘FPGA platform’ ?
ANS : Emulation word sound similar to simulation and work similar to that also. In simulation compiler break the code into nodes and calculate the value of each node at each clock edge. Emulation platform is actually group of processors which make can separate thread for each node. It work on synthesized design. Emulation platform is a hardware so we can connect debugger and other peripherals with it.
It is similar to FPGA but have following differences
  1. Capacity : Emulation Platform has very large capacity compare to FPGA. You can emulate full Soc in emulation platform.
  2. Speed : Emulation platform work on KHz to few MHz whereas FPGA work on 10 to 100 MHz. So FPGA are 100 times faster than Emulation.
  3. Debug : Emulation platform gives facility to take waveform dump at anytime at any trigger condition, but FPGA you need to add extra logic plus select the signal previously which we want to check.
  4. Force : In emulation we can force any value to any signal but in FPGA we can not do this.
  5. Timing : In FPGA we need to do Place and Route after synthesis but in Emulation platform we need not to do P&R.

  1. What is the difference between ‘rtl simulation’ and ‘netlist simulation’ ?
ANS : In simulation compiler do and don’t do the following operation
  1. Do the syntax check
  2. Don’t optimize the code
  3. Don’t synthesize the code means non-synthesizable construct can be use in simulation, eg. delay, initial, fork join etc.
  4. Do break the code into nodes and calculate the value of each node for each clock edge. So as your design increases, number of nodes increases and hance take more time to run complete simulation. Also it dumps the waveform for each clock edge.
  5. Don’t change the signal name.
In RTL simulation, tool compile the code and determine the nodes and dump the value of each nodes at each clock cycle. Whereas netlist generate after the synthesis in which RTL code is optimized and change into gate level. This increase the number of nodes and take more time in simulation compared to RTL simulation.

36. Which one of following is not synthesizable VHDL statement  ?
  1. ‘case’
  2. ‘wait until’
  3. ‘wait for’
  4. ‘generate’
ANS : ”wait for” is non synthesizable.
Under process ‘wait until’ is synthesizable.

Thursday, April 7, 2016

user constraint file fpga

Sometime we may required or need to control the placing the modules, particular PIN muxing, some timing directives in the FPGA design. We can do it by passing ‘Constraint File’ to the tool along with rtl files. In constraint file we can write following constraint -
• Grouping Constraints
• Logical Constraints
• Physical Constraints
• Mapping Directives
• Placement Constraints
• Routing Directives
• Synthesis Constraints
Timing Constraints
• Configuration Constraints


Most of tool vendors have their own set of way of writing these constraints. Example Xilinx ISE has with file extension “.ucf” (User Constraint File), Synopsis has different and so on. Here we briefly discuss some important and frequently used design constraints used in Xilinx ISE.


First discuss the elements which frequently used in constraint file i.e. INST, NET and PIN.
  1. An INST (instance) - it refers to a primitive instance (like a flip-flop or BRAM or SRL or LUT) or to a hierarchical instance (the instantiation of a module/entity).
  2. A PIN (pin on an instance) - either a primitive instance or a hierarchical instance. So the D and Q on a flip-flop are pins. Also when you instantiate a module/entity that has a port (named A), when the module/entity is instantiated, the instance has a PIN named A.
  3. A NET is something that connects pins together.


Let’s discuss most important constraint in FPGA Prototyping which is “Timing Constraint”.
Timing specification can be applied to entire device or PIN or NET or INST or to specific group in design. Here some examples
# Define Period
NET  “sys_clk”  TNM_NET  =  “sys_clk” ;
TIMESPEC “TS_sys_clk”  =  PERIOD “sys_clk” 10 ns  HIGH  50% ;


# Related Clock
NET “sys_clk_2”  TNM_NET  =  “sys_clk_2” ;
TIMESPEC “TS_sys_clk_2”  =  PERIOD  “sys_clk_2”  “TS_sys_clk” * 2 ;


# Related Phased Clock
NET “sys_clk_90”  TNM_NET  =  “sys_clk_90” ;
TIMESPEC “TS_sys_clk_90”  =  PERIOD  “sys_clk_90”  “TS_sys_clk”  * 1 PHASE + 2.5ns ;
# Generated Clock
NET  “sys_clk_gen”  TNM_NET  =  “sys_clk_gen” ;
TIMESPEC  “TS_sys_clk_gen”  =  PERIOD  “TS_sys_clk” * 1 ;


# OFFSET
#• The first, global OFFSET applies to all inputs or outputs for a specific clock.
#• The second, a group OFFSET form, identifies a group of inputs or outputs clocked by a common clock that have the same timing requirements.
#• The third, a specific OFFSET form, specifies the timing by each input or output.


# Examples
NET  sig*  OFFSET  =  IN  <value units>  BEFORE <clock_pad_net>  ;
# ‘value unit’ time allowed for data to propagate from pad to meet a setup requirement to clock.


NET  sig*  OFFSET  =  OUT  <value units>  AFTER  <clock_pad_net>  ;
# ‘value unit’ time allowed for data to propagate from synchronous element (clock to out) to pad.


# From PAD to PAD
TIMESPEC “TS_p2p”  =  FROM  “pad”  TO  “pad”  10 ns ;


# When some net or paths are timing independent or mutually exclusive timing then we define those as “FALSE PATH”. It help tool to place those nets or paths which are time critical. Ex.


NET  “net_name”  TIG  ;
INST  “inst_name”  TIG  ;
PIN  “instance.pin_name”  TIG  ;


# FALSE PATH by TIMING PATH
TIMESPEC  “TSid”  =  FROM  “from_grp”  TO  “to_grp”  TIG ;
TIMESPEC  “TSid”  =  FROM  “from_grp”  THRU  “thru_pt”  TO  “to_grp”  TIG ;


# MULTI CYCLE PATH and SLOW FAST EXCEPTIONS
TIMESPEC “TS_sys_clk1_to_sys_clk2”  =  FROM “sys_clk1”  TO  “sys_clk2”  20 ns ;


There are three basic method for creating groups
  1. By Connectivity
    1. NET  “net_name”   TNM_NET  =  qualifier  “tnm_name” ;
  2. By Hierarchy
    1. INST “inst_name”  TNM  =  qualifier  “tnm_name” ;
  3. By Element


An optional qualifier of FFS, PADS, RAMS, BRAMS_PORTA, BRAMS_PORTB, CPUS,
MULTS, HSIOS or LATCHES may be used.


# Group Elements By Element Output Net Name Schematic User (TIMEGRP)
TIMEGRP  identifier  =  element  (output_netname) ;
  • identifier is the name for the new time group.
  • element can be FFS, All Pads, Input Pads, Output Pads, Bi-directional Pads, 3-stated Output Pads, RAMs, LATCHES, or User Groups.
  • output_netname is the name of the net attached to the element.
Eg.
TIMEGRP  FF_grp  =  FFS (“U1/*”) ;


After ISE now Xilinx has launched new powerful tool for newer FPGA Like Virtex-7 or higher has named Xilinx Vivado and now major industry using this for FPGA Prototyping. It uses XDC file instead of UCF, it has lot more capability than UCF. We can easily change syntax for XDC from UCF.


UCF (User Constraint File)
XDC (Xilinx Design Constraint)
TIMESPEC PERIOD
create_clock
OFFSET IN
set_input_delay
OFFSET OUT
set_output_delay
TIG
set_false_path
FROM/THRU/TO
Set_multicycle_path
set_max_delay/set_min_delay
TNM
create_path_group
INST “X” LOC =
set_property LOC



# Define Period
create_clock  -name  sys_clk  -period  10  [get_ports  sys_clk]


# Define Period with HIGH 40% and input Jitter 200ps
create_clock  -name  sys_clk  -period  10  - waveform {0.0 4}  [get_ports  sys_clk]
set_input_jitter  0.2  [get_clocks  sys_clk]


# Generated Clock
create_generated_clock  -name  sys_clk_2  -source  sys_clk  -divide_by  2  sys_clk_2
or
create_generated_clock  -name  sys_clk_2  -source  sys_clk  edges  {1,3,5} sys_clk_2


# OFFSET
# Input Delay
set_input_delay  -max 7  -clock  clock_input  [get_ports  input_data*]
set_input_delay  -min 3  -clock  clock_input  [get_ports  input_data*]
# Output Delay
set_output_delay  -max 4  -clock  clock_input  [get_ports  output_data*]


# False Path
set_false_path  -from  [get_clocks  sys_clk]   -to  [get_clocks  jtag_clk]
set_false_path  -through  [get_pins  MUX/S]


# Asynchronous/Exclusive Clock Groups
set_clock_groups  -physically_exclusive  -group  [get_clocks CLK0]  -group  [get_clocks CLK1]
set_clock_groups  -asynchronous -group [get_clocks CLK0]  -group  [get_clocks CLK1]


# Multicycle Paths - setup and hold
____________   multicycle path = 2T ____________
|      REGA |   -----------------------------> |     REGB |
|Q          D|-----<_Combo_logic_>------|Q           D|
| | | |
| ---|> |     |----|> |
| |__________ |     | |__________|
CLK____|________________________________ |


set_multicycle_path  -from  REGA/CLK  -to  REGB/D  2
set_multicycle_path  -from  REGA/CLK  -to  REGB/D  2  -hold 1

# Physical Constraint

set_property  LOC  H18  [get_nets  RESET]

Complete Soon !!